The objective of this WP is to provide up-to-date HPC-hardware or – if not available at the involved HPC-centres – to provide access to such resources. Furthermore adequate tools – when indicated hardware-specific – for program development will be provided to enable developers to implement the new codes for future supercomputers.
On the one hand this WP will provide access to the HPC architectures currently available at the participating sites ('traditional' x86 and GPUs, using Infiniband, sgi UV) and scheduled for installation during the project (Intel IVB, Nvidia Kepler using Aries interconnet, later Intel Haswell
and possible Intel MIC and/or Nvida accelerators). Resources not available at participating HPC centers will be localized at other sites and – if possible – also be provided to the other WPs. These could include, but are not limited to, systems using low power CPUs (e.g. ARM, IBM BlueGene) or using specialized networks, e.g., providing global Address space or efficient hardware to support partitioned global address space (e.g. the NUMA links on the SGI UV or the Cray Aries interconnect).
On the other hand and taking into account the hardware solutions currently available, the current state-of-the-art of software tools necessary for developers, such as more recent programming models (PGAS, OpenACC, hybrid MPI/OpenMP), specialized compilers and debuggers or mathematical libraries optimized for the specific developments in NUMEXAS, will be made available to the code developers in the project.
At least for the Cray systems at HLRN power measurement tools will be available. These tools will be used to measure the energy consumption of simulation runs.
Task leader: CESCA. Partners involved: CESCA, LUH-HLRN
Numerical libraries will be evaluated, whether they are suited for the hardware used. First of all Trilinos will be used, since this library is used by software packages from WPs 4-7. If necessary, other libraries will be evaluated (for example PETSc or vendor-specific libraries). Trilinos package Tpetra has an interface to many core processors including GPUs. In case Intel Xeon Phi (MIC) processors will be installed at one of the HPC sites, we intend – if necessary - to collaborate closely with the hardware vendor and the Trilinos team to port this interface to MICs.
These results should help developers from the other WPs to implement codes which can exploit the next generation of HPC hybrid systems.
Emphasis will be put in the identification of commonalities (as described in section B1.1.4 of the DoW) at algorithmic and software levels that can be of general interest and applicability for other HPC developments.
Task leader: CESCA. Partners involved: CIMNE, CESCA, LUH-HLRN
Lead beneficiary. CESCA
Lead beneficiary: LUH
Lead beneficiary: LUH